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ISL6264
Data Sheet October 16, 2006 FN6359.1
Two-Phase Core Controller for AMD Mobile Turion CPUs
The ISL6264 is a two-phase buck converter regulator with embedded gate drivers. The two-phase buck converter uses two interleaved channels to effectively double the output voltage ripple frequency and thereby reduce output voltage ripple amplitude with fewer components, lower component cost, reduced power dissipation, and smaller real estate area. ISL6264 can also be configured as single-phase controller for low power CPU applications. The heart of the ISL6264 is the patented R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. Compared with the traditional multi-phase buck regulator, the R3 TechnologyTM has the fastest transient response. This is due to the R3 modulator commanding variable switching frequency during a load transient. To boost battery life, the ISL6264 supports PSI_L for deeper sleep mode via automatically enabling different operation modes. At heavy load operation of the active mode, the regulator commands the two phase continuous conduction mode (CCM) operation. While the PSI_L is asserted during the deeper sleep mode, the ISL6264 smoothly disables one phase and operates in a one-phase diode emulation mode (DE) to maximize the efficiency at light load. A 6-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.375V to 1.55V. A 0.5% system accuracy of the core output voltage over temperature at active mode is achieved by the ISL6264. A unity-gain differential amplifier is provided for remote CPU die sensing. This allows the voltage on the CPU die to be accurately measured and regulated per AMD mobile CPU specifications. Current sensing can be realized using either lossless inductor DCR sensing or precision resistor sensing. A single NTC thermistor network thermally compensates the gain and the time constant of the DCR variations.
Features
* Precision Two-phase Core Voltage Regulator - 0.5% system accuracy over temperature * Voltage positioning with Adjustable Load Line and Offset * Internal Gate Driver with 2A Driving Capability * Dynamic Phase Adding/Dropping * Differential Current Sensing: DCR or resistor * Microprocessor Voltage Identification Input - 6-Bit VID Input - 0.775V to 1.55V in 12.5mV Steps - 0.375V to 0.7625V in 25mV Steps * Adjustable Reference-Voltage Offset * Audio Filter Enable/Disable * User Programmable Switching Frequency * Differential Remote CPU Die Voltage Sensing * Static and Dynamic Current Sharing * Overvoltage, Undervoltage, and Overcurrent Protection
Ordering Information
PART NUMBER (Note) ISL6264CRZ PART MARKING TEMP (C) PACKAGE (Pb-Free) PKG. DWG. #
ISL6264CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6264CRZ-T ISL6264CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6264 Pinout
ISL6264 (40 LD 6x6 QFN) TOP VIEW
PGOOD BOOT1 31 30 UGATE1 29 PHASE1 28 PGND1 27 LGATE1 GND PAD (BOTTOM) 26 PVCC 25 LGATE2 24 PGND2 23 PHASE2 22 UGATE2 21 BOOT2 11 RTN 12 DROOP 13 DFB 14 VO 15 VSUM 16 VIN 17 GND 18 VDD 19 ISEN2 20 ISEN1 VR_ON PSI_L VID5 VID4 VID3 VID2 VID1 33 VID0 32
40 SET RBIAS OFS SOFT OCSET VW COMP FB VDIFF VSEN 1 2 3 4 5 6 7 8 9 10
39
38
37
36
35
34
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FN6359.1 October 16, 2006
ISL6264
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE). . . . . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . . . PHASE -0.3V (DC) to BOOT PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V -2.5V (<20ns Pulse Width, 5J) to VDD+0.3V ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . -0.3 - +7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 32 4 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V 5% Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10C to +100C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150C junction may trigger the shutdown of the device even before 150C, since this number is specified as typical.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
SYMBOL INPUT POWER SUPPLY IVDD +5V Supply Current
VDD = 5V, TA = -10C to +100C, Unless Otherwise Specified. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
VR_ON = 3.3V VR_ON = 0V
3.9
3.1 4.35 4.1
3.6 1 1 4.5 -
mA A A V V
IVIN PORr PORf
Battery Supply Current at VIN pin POR (Power-On Reset) Threshold
VR_ON = 0V, VIN = 25V, VDD Rising VDD Falling
SYSTEM AND REFERENCES %Error (VDD_core) System Accuracy No load, closed loop, active mode, TA = +25C to +100C, VID = 0.75-1.55V VID = 0.425-0.75V VID = 0.375-0.425V RRBIAS VDD_core (max) VDD_core (min) RBIAS Voltage Maximum Output Voltage Minimum Output Voltage RRBIAS = 147k VID = [000000] VID = [111111] -0.5 -2 -4 1.5 1.52 1.55 0.375 0.5 +2 +4 1.54 % % % V V V
CHANNEL FREQUENCY fSW Nominal Channel Frequency Adjustment Range AMPLIFIERS Droop Amplifier Offset AV0 GBW SR Error Amp DC Gain (Note 3) Error Amp Gain-Bandwidth Product (Note 3) Error Amp Slew Rate (Note 3) CL = 20pF CL = 20pF -0.3 90 18 5.0 0.3 mV dB MHz V/s RFSET = 6.81k, 2 channel operation, Vcomp = 2V 285 200 300 315 500 kHz kHz
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FN6359.1 October 16, 2006
ISL6264
Electrical Specifications
SYMBOL ISEN1, ISEN2 Imbalance Voltage Input Bias Current SOFT START CURRENT ISS I2 Soft Start Current Soft Current during VID on the Fly -48 185 -43 210 -38 235 A A 20 1 mV nA VDD = 5V, TA = -10C to +100C, Unless Otherwise Specified. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
GATE DRIVER DRIVING CAPABILITY RSRC(UGATE) UGATE Source Resistance (Note 4) ISRC(UGATE) UGATE Source Current (Note 4) 500mA Source Current VUGATE_PHASE = 2.5V 500mA Sink Current VUGATE_PHASE = 2.5V 500mA Source Current VLGATE = 2.5V 500mA Sink Current VLGATE = 2.5V 1 2 1 2 1 2 0.5 4 1 1.5 1.5 1.5 0.9 A A A A k
RSNK(UGATE) UGATE Sink Resistance (Note 4) ISNK(UGATE) UGATE Sink Current (Note 4)
RSRC(LGATE) LGATE Source Resistance (Note 4) ISRC(LGATE) LGATE Source Current (Note 4)
RSNK(LGATE) LGATE Sink Resistance (Note 4) ISNK(LGATE) Rp(UGATE) LGATE Sink Current (Note 4) UGATE to PHASE Resistance
GATE DRIVER SWITCHING TIMING (refer to timing diagram) tRU tRL tFU tFL tPDHU tPDHL UGATE Rise Time (Note 3) LGATE Rise Time (Note 3) UGATE Fall Time (Note 3) LGATE Fall Time (Note 3) UGATE Turn-on Propagation Delay LGATE Turn-on Propagation Delay PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, Outputs Unloaded PVCC = 5V, Outputs Unloaded 23 7 8.0 8.0 8.0 4.0 30 15 44 30 ns ns ns ns ns ns
BOOTSTRAP DIODE Forward Voltage Leakage POWER GOOD and PROTECTION MONITOR VOL IOH tpgd OVH OVHS PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay Over-voltage Threshold Severe Over-voltage Threshold OCSET Reference Current OC Threshold Offset Current Imbalance Threshold UVf Under-voltage Threshold (VDIFF-SOFT) IPGOOD = 4mA PGOOD = 3.3V VR_ON Enable to PGOOD High when Csoft = 47nF VO rising above setpoint >1ms VO rising above setpoint >0.5s Rbias = 147k DROOP rising above OCSET >120s Difference between ISEN1-ISEN2 >1ms VO falling below setpoint for >1ms -1 6.3 155 1.775 10 -3 -300 0.11 7.6 195 1.8 10.2 8 -250 0.4 1 8.9 235 1.825 10.4 3 -200 V A ms mV V A mV mV mV VDDP = 5V, Forward Bias Current = 2mA VR = 16V 0.43 0.58 0.67 1 V A
OFFSET FUNCTION IOFFSET IFB OFS Pin Current FB Pin Souring Current 36.5k resistor connects OFS pin to GND. 33 33 A A
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FN6359.1 October 16, 2006
ISL6264
Electrical Specifications
SYMBOL LOGIC INPUTS VIL(3.3V) VIH(3.3V) IIL(3.3V) IIL(3.3V) VIL(3.3V) VIH(3.3V) IIL(3.3V) IIL(3.3V) VIL(1.0V) VIH(1.0V) IIL(1V) DAC(VID0-VID5) and PSI_L input low DAC(VID0-VID5), PSI_L input high Leakage current of DAC(VID0-VID5) Logic input is low and PSI_L Logic input is high at 1V SET SET Leakage current of SET Logic input is low Logic input is high at 3.3V VR_ON VR_ON Leakage current of VR_ON Logic input is low Logic input is high at 3.3V 2.3 -1 2.3 -1 0.7 -1 0 0 0 0.45 0 0.45 1 1 1 1 0.3 1 V V A A V V A A V V A A VDD = 5V, TA = -10C to +100C, Unless Otherwise Specified. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
NOTES: 3. Guaranteed by design. 4. Guaranteed by characterization.
ISL6264 Gate Driver Timing Diagram
PWM tPDHU tRU UGATE LGATE 1V tFL tPDHL tRL tFU 1V
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FN6359.1 October 16, 2006
ISL6264 Functional Pin Description
PGOOD VR_ON BOOT1 PSI_L VID5 VID4 VID3 VID2 VID1 VID0
FB
This pin is the inverting input of the error amplifier.
VDIFF
This pin is the output of the differential amplifier.
30 UGATE1 29 PHASE1 28 PGND1 27 LGATE1
40 39 38 37 36 35 34 SET RBIAS OFS SOFT OCSET VW COMP FB VDIFF 1 2 3 4 5 6 7 8 9 GND PAD (BOTTOM)
33 32 31
VSEN
Remote core voltage sense input.
RTN
Remote core voltage sense return.
26 PVCC 25 LGATE2 24 PGND2 23 PHASE2 22 UGATE2 21 BOOT2
DROOP
Output of the droop amplifier. The voltage level at this pin is the sum of Vo and the programmed droop voltage by the external resistors.
VSEN 10 11 RTN 12 13 14 15 16 17 DROOP VSUM GND DFB VIN VO 18 19 20 ISEN2 ISEN1 VDD
DFB
This pin is the inverting input of the droop amplifier.
VO
An input to IC reporting the local output voltage.
VSUM SET
Logic low enables the audio filter which only allows above 20kHz operation. Logic high disables the audio filter. This pin is connected to the summation junction of channel current sensing.
VIN
It is used for input voltage feed forward to improve input line transient performance.
RBIAS
147k resistor to GND sets internal current reference, ~10A, for the overcurrent protection setting.
GND
Signal ground. Connect to local controller ground.
OFS
A resistor from this pin to GND programs a DC current source for generating a positive offset voltage across the resistor between FB and VDIFF pins. The OFS pin voltage is 1.2V.
VCC
5V bias power supply for the ISL6264 controller.
ISEN2
Individual current sharing sensing for channel 2.
SOFT
A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the non-inverting input of the error amplifier. A 210A internal current source is generated to charge or discharge the SOFT pin capacitor to determine the slew-rate of VID. During the start-up process, the current source is reduced to 43A.
ISEN1
Individual current sharing sensing for channel 1.
BOOT2
This pin is the upper gate driver supply voltage for phase 2. An internal boot strap diode is connected to the PVCC pin.
OCSET
Overcurrent protection set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10A current source is connected internally to this pin.
UGATE2
Upper MOSFET gate signal for phase 2.
PHASE2
The phase node of phase 2. This pin should connect to the source of upper MOSFET. It is the return path for the upper MOSFET drive.
VW
A resistor from this pin to COMP programs the switching frequency (for example, 6.81k ~ 300kHz).
COMP
This pin is the output of the error amplifier.
PGND2
The return path of the lower gate driver for phase 2.
LGATE2
Lower-side MOSFET gate signal for phase 2. 6
FN6359.1 October 16, 2006
ISL6264
PVCC
5V power supply for gate drivers.
LGATE1
Lower-side MOSFET gate signal for phase 1.
PGND1
The return path of the lower gate driver for phase 1.
PHASE1
The phase node of phase 1. This pin should connect to the source of upper MOSFET. It is the return path for the upper MOSFET drive.
UGATE1
Upper MOSFET gate signal for phase 1.
BOOT1
This pin is the upper gate driver supply voltage for phase 1. An internal boot strap diode is connected to the PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5
VID input with VID0 is the least significant bit (LSB) and VID5 is the most significant bit (MSB).
VR_ON
A high level logic signal on this pin enables the ISL6264.
PSI_L
Sleeper mode indicator. When asserted low, ISL6264 initiates the single-phase operation.
PGOOD
Power good open-drain output. Will be pulled up externally by a resistor to Vccp or 3.3V.
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FN6359.1 October 16, 2006
RBIAS VCC
PGOOD ISEN1 ISEN2 VIN PVCC
VO VIN FLT PVCC
VID0
Function Block Diagram
8
CURRENT BALANCE DAC
Dacout I_BALF
PVCC
VID1
VID2 Pgood
PGOOD MONITOR AND LOGIC
VID3
FAULT AND PGOOD LOGIC
VID4
VID5 CH1
MODE CHANGE REQUEST
BOOT CH1 CH2 PHASE1 OC VIN VSOFT
VO
PHASE CONTROL LOGIC MODULATOR
FLT
UGATE1
VR_ON
DRIVER LOGIC
PVCC
PSI_L
SINGLE PHASE
MODE CONTROL SOFT
SINGLE PHASE
LGATE1
ISL6264
10uA
0.5
OCSET
+
OC VIN VO Vw
PHASE SEQUENCER
CH2 OC VIN VSOFT
ULTRASONIC TIMER
PGND1
PVCC
BOOT2
FLT
UGATE2
VO
DROOP VSOFT
MODULATOR
PHASE2
DFB
+ +
+ + E/A
Audio Filter
DRIVER LOGIC 1+
PVCC
FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6264
VO
DROOP
LGATE2
1 + +1 -
-
1.2V
VCC
PGND2
1
Vw
+ OFS
VSEN RTN
VDIFF
SET SOFT FB
COMP
VW
GND
FN6359.1 October 16, 2006
ISL6264 Simplified Application Circuit for DCR Current Sensing
V+5 V IN
PVCC
VDD
VIN
R 12
RBIAS
VIN
C7
ISL6264
C8
SOFT
UGATE1 BOOT1 PHASE1
C6 R
LO
VID<0:5>
R ofs
VIDs OFS
LGATE1
L
CL
DNP ISEN2
PSI_L SET
ISEN2
PSI_L
PGND1 ISEN1 VO
R8
VSUM
VO CO
Cf
SET
VR_ON CPU_PWRGD Remote Sense
R2 R3 C3
VR_ON PGOOD VSEN RTN VDIFF UGATE2 BOOT2 PHASE2 LGATE2
C1 C2 R1 C5
VIN
C8
LO
DNP
RL R9
VSUM ISEN1
CL
ISEN1
FB COMP
PGND2 ISEN2 DROOP VSUM OCSET
VSUM
VO
RFSET
VW
C9
GND
DFB
R5
R6 R4 C4
RN
NTC Network
CCS
VO
FIGURE 2. ISL6264 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
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FN6359.1 October 16, 2006
ISL6264 Simplified Application Circuit for Resistor Current Sensing
V+5 V IN
PVCC
VDD
VIN
R 12
RBIAS
VIN
C7
ISL6264
C8
SOFT
UGATE1 BOOT1 PHASE1
C6
LO
Rsense
VID<0:5>
R ofs
VIDs OFS
R
LGATE1
L
CL
PSI_L
PSI_L
PGND1 ISEN1 VO
R8
ISEN2
VSUM
VO CO
Cf
SET
SET
VR_ON CPU_PWRGD Remote Sense
R2 R3 C3
VR_ON PGOOD VSEN RTN VDIFF UGATE2 BOOT2 PHASE2 LGATE2
C1 C2 R1 C5
VIN
C8
LO
Rsense
RL R9
VSUM ISEN1
CL
FB COMP
PGND2 ISEN2 DROOP VSUM OCSET
VSUM
VO
RFSET
VW
C9
GND
DFB
R5
R6 R4 C4
RN
CCS
VO
FIGURE 3. ISL6264 BASED TWO-PHASE BUCK CONVERTER WITH RESISTOR CURRENT SENSING
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FN6359.1 October 16, 2006
ISL6264 Typical Performance Curves
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 IOUT (A) 25 30 35 40 VIN = 19.0V VIN = 12.6V VIN = 8.0V VOUT (V)
(0.36H filter inductor, 4 x 330F output SP caps and 32 x 22F ceramic caps)
1.16 1.15 1.14 1.13 1.12 VIN = 12.6V 1.11 1.1 1.09 1.08 1.07 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IOUT (A) VIN = 19.0V VIN = 8.0V
FIGURE 4. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM, PSI_l = HIGH, VID = 1.15V
FIGURE 5. ACTIVE MODE LOAD LINE, 2 PHASE, CCM, PSI_L = HIGH, VID = 1.15V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 IOUT (A) 15 20 VIN = 8.0V VIN = 12.6V VIN = 19.0V VOUT (V)
1.155 1.15 1.145 1.14 1.135 1.13 1.125 1.12 1.115 1.11 0 2 4 6 8 10 12 IOUT (A) 14 16 18 20 VIN = 19.0V VIN = 8.0V VIN = 12.6V
FIGURE 6. ACTIVE MODE EFFCIENCY, 1 PHASE, DE, PSI_L = LOW, VID = 1.15V
FIGURE 7. ACTIVE MODE LOAD LINE, 1 PHASE, DE, PSI_L = LOW, VID = 1.15V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 IOUT (A) 10 VIN = 19.0V VOUT (V) VIN = 12.6V VIN = 8.0V
0.964 0.954 0.944 0.934 0.924 0.914 0.904 0 2 3 IOUT (A) 4 5 6 VIN = 12.6V
VIN = 19.0V VIN = 8.0V
FIGURE 8. EFFICIENCY OF 1-PHASE DE MODE, PSI_l = LOW. DCM MODE, VID = 0.9V, OFFSET = 33mV
FIGURE 9. 1-PHASE DE MODE LOAD LINE, PSI_l = LOW, VID = 0.9V, OFFSET = 33mV
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FN6359.1 October 16, 2006
ISL6264 Typical Performance Curves
VR_ON
(0.36H filter inductor, 4 x 330F output SP caps and 32 x 22F ceramic caps) (Continued)
VR_ON
Vo
Vo
PGOOD
PGOOD
FIGURE 10. SOFT START WAVEFORM AT VID = 1.55V, ILOAD = 0A
FIGURE 11. PRE-BIASED VO SOFT START AT VID = 1.55V, ILOAD = 0A
Vo IL1, IL2
IL1
IL2
Vo
Phase1
FIGURE 12. SOFT START WAVEFORM SHOWING CURRENT SHARING AT VIN = 12.6V, VID = 1.2V AND ILOAD = 36A
FIGURE 13. PHASE CURRENT BALANCE, ILOAD = 36A AND VID = 1.55V
Vo
Vo
Phase 1
Phase 1
Vin
Vin
FIGURE 14. 8V TO19V INPUT LINE TRANSIENT RESPONSE AT ILOAD = 5A AND VID = 1.15V FIGURE 15. 19V TO >8V INPUT LINE TRANSIENT RESPONSE AT ILOAD = 5A AND VID = 1.15V
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FN6359.1 October 16, 2006
ISL6264 Typical Performance Curves
(0.36H filter inductor, 4 x 330F output SP caps and 32 x 22F ceramic caps) (Continued)
Io COMP
Vo
Io
Vo
COMP Phase1
Phase1
FIGURE 16. LOAD APPLICATION RESPONSE AT 2-PHASE CCM, VIN = 19V, ILOAD = 10A46A, AND VID = 1.15V FIGURE 17. LOAD RELEASE RESPONSE AT 2-PHASE CCM, VIN = 19V, ILOAD = 46A10A, AND VID = 1.15V
Vo
Vo
COMP
Phase1
COMP
Phase1
FIGURE 18. LOAD APPLICATION RESPONSE AT 1-PHASE DE MODE, ILOAD = 4A19A, PSI_L = 0, AND VID = 1V
FIGURE 19. LOAD RELEASE RESPONSE AT 1-PHASE DE MODE, ILOAD = 19A4A, PSI_L = 0, AND VID = 1V
Ch1:soft
Ugate
Ch2: Vo
Lgate
VID4 PGOOD
FIGURE 20. VID TRANSITION RESPONSE AT 2-PHASE CCM MODE, VIN = 12.6V AND VID = 1.55V 1.15V
FIGURE 21. GATE DRIVER WAVEFORMS AT VIN = 8V, ILOAD = 40A, 2-PHASE MODE. 2 X IRF7821 AS UPPER DEVICE AND 2 X IRF7832 AS LOWER DEVICE
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FN6359.1 October 16, 2006
ISL6264 Typical Performance Curves
Ugate
(0.36H filter inductor, 4 x 330F output SP caps and 32 x 22F ceramic caps) (Continued)
Lgate
Phase1
FIGURE 22. GATE DRIVER WAVEFORMS AT VIN = 8V, ILOAD = 40A, 2 X IRF7821 AS UPPER MOSFET AND 2 X IRF7832 AS LOWER MOSFET
FIGURE 23. PHASE NODE JITTER PERFORMANCE AT VIN = 19V, ILOAD = 40A AND VID = 1.55V
Vo Vo PSI_L Phase1 PSI_L
Phase1 Phase2
Phase2
FIGURE 24. DEEPER SLEEP MODE ENTRY WITH PSI_L TOGGLING FROM HIGH TO LOW AND VID FROM 1.15V TO 0.95V
FIGURE 25. DEEPER SLEEP MODE EXIT WITH PSI_L TOGGLING FROM LOW TO HIGH AND VID FROM 0.95V TO 1.15V
Vo
Vo
PSI_L Phase1
PSI_L
Phase1 Phase2 Phase2
FIGURE 26. TRANSITION FROM 1-DE TO 2-CCM VIA PSI_L TOGGLING FROM LOW TO HIGH AND ILOAD = 2A FIGURE 27. TRANSITION FROM 2-CCM TO 1-DE VIA PSI_L TOGGLING FROM HIGH TO LOW AND ILOAD = 2A
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FN6359.1 October 16, 2006
ISL6264 Theory of Operation
The ISL6264 is a two-phase regulator providing the power to AMD Mobile CPUs such as Turion CPUs and includes integrated gate drivers for reduced system cost and board area. The regulator provides optimum steady-state and transient performance for microprocessor core applications up to 50A. System efficiency is enhanced by idling a phase at low-current and implementing automatic DCM-mode operation when PSI_L is asserted to logic low. The heart of the ISL6264 is the R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. The ISL6264 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulse widths. Operating on these large-amplitude, noise-free synthesized signals allows the ISL6264 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6264 has an error amplifier that allows the controller to maintain a 0.5% voltage regulation accuracy throughout the VID range from 0.75V to 1.55V. The hysteresis window voltage is relative to the error amplifier output such that load current transients results in increased switching frequency, which gives the R3 regulator a faster response than conventional fixed frequency PWM controllers. Transient load current is inherently shared between active phases due to the use of a common hysteretic window voltage. Individual average phase voltages are monitored and controlled to equally share the static current among the active phases.
VDD
VR_ON 100s SOFT AND Vo
dV 43A ------- -------------dt C soft
~7.6ms PGOOD
FIGURE 28. SOFT START WAVEFORMS
Static Operation
After the start sequence, the output voltage will be regulated to the value set by the VID inputs per Table 1. The entire VID table is presented in the AMD specification.The ISL6264 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V.
TABLE 1. VID TABLE FOR AMD 6-BIT VID CPU VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 VOUT (V) 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0000 0.9750 0.9500 0.9250
Start-up Timing
With the controller's +5V VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic HIGH threshold. Approximately 100s later, SOFT and VOUT begin ramping toward the final VID voltage. At startup, the regulator always operates in a 2-phase CCM mode, regardless of PSI_L control signal assertion levels. During this internal, the SOFT cap is charged by 43A current source. If the SOFT capacitor is selected to be 47nF, the SOFT ramp will be at 0.9mV/s slewrate. Once VOUT is within 10% of the VID voltage, approximately 7ms later, PGOOD is asserted HIGH. Typical start-up timing is shown in Figure 28. The SOFT cap is charged/discharged by approximate 200A after the start-up. Therefore, VOUT slews at about 4mV/s to the voltage set by the VID pins.
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TABLE 1. VID TABLE FOR AMD 6-BIT VID CPU (Continued) VID5 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 Operation
A fully-differential amplifier implements core voltage sensing for precise voltage control at the microprocessor die. The inputs to the amplifier are the VSEN and RTN pins. As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to current to achieve the proper load line. The ISL6264 provides for current to be measured using either resistors in series with the channel inductors as shown in the application circuit of Figure 3, or using the intrinsic series resistance of the inductors as shown in the application circuit of Figure 2. In both cases signals representing the inductor currents are summed at VSUM, which is the non-inverting input to the DROOP amplifier shown in the block diagram of Figure 1. The voltage at the DROOP pin minus the output voltage, VO, is a high-bandwidth analog of the total inductor current. This voltage is used as an input to a differential amplifier to achieve the load line, and also as the input to the overcurrent protection circuit. When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load-line accuracy. In addition to monitoring the total current (used for DROOP and overcurrent protection), the individual channel average currents are also monitored and used for balancing the load between channels. The IBAL circuit will adjust the channel pulse-widths up or down relative to the other channel to cause the voltages presented at the ISEN pins to be equal. The ISL6264 controller can be configured for two-channel operation, with the channels operating 180 apart. The channel PWM frequency is determined by the value of RFSET connected to pin VW as shown in Figure 2 and Figure 3. Input and output ripple frequencies will be the channel PWM frequency multiplied by the number of active channels.
TABLE 2. PSI_l = LOGIC HIGH 2-CCM PSI_L = LOGIC LOW 1-DE (diode emulation)
High Efficiency Operation Mode
The ISL6264 has two operating modes to optimize efficiency. The controller's operational modes are designed to work in conjunction with the PSI_L control signals to maintain the optimal system configuration. These operating modes are established as shown in Table 2. At high current levels, the system will operate with both phases fully active, responding rapidly to transients and deliver the maximum power to the load. At reduced load current levels, one of the phases may be idled. This configuration will minimize switching losses, while still maintaining transient response capability. At the lowest current levels, the controller automatically configures the system to operate in single-phase automatic-DCM
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mode, thus achieving the highest possible efficiency. In this mode of operation, the lower FET will be configured to automatically detect and prevent discharge current flowing from the output capacitor through the inductors, and the switching frequency will be proportionately reduced, thus greatly reducing both conduction and switching losses. Smooth mode transitions are facilitated by the R3 TechnologyTM, which correctly maintains the internally synthesized ripple currents throughout mode transitions. The controller is thus able to deliver the appropriate current to the load throughout mode transitions. The controller contains embedded mode-transition algorithms which robustly maintain voltage-regulation for all control signal input sequences and durations. Mode-transition sequences will often occur in concert with VID changes; therefore the timing of the mode transition of ISL6264 has been carefully designed to work in concert with VID changes. For example, transitions into single-phase mode if PSI_L and VID toggles at the same time will be delayed until the VID induced voltage ramp is complete, to allow the associated output capacitor charging current is shared by both inductor paths. While in single-phase automatic-DCM mode with PSI_L = logic low, VID changes will initiate an immediate return to two-phase CCM mode during the VID transition. This ensures that both inductor paths share the output capacitor charging current and are fully active for the subsequent load current increases. The controller contains internal counters which prevent spurious control signal glitches from resulting in unwanted mode transitions. Control signals of less than two switching periods do not result in phase-idling. Signals of less than seven switching periods do not result in implementation of automatic-DCM mode. While transitioning to single-phase operation, the controller smoothly transitions current from the idling-phase to the active-phase, and detects the idling-phase zero-current condition. During transitions into automatic-DCM or forced-CCM mode, the timing is carefully adjusted to eliminate output voltage excursions. When a phase is added, the current balance between phases is quickly restored.
Dynamic Operation
The ISL6264 responds to changes in VID command voltage by slewing to new voltages with a dV/dt set by the SOFT capacitor. The internal current source of 230A is used to charge or discharge the SOFT capacitor. Intersil's R3 TechnologyTM has intrinsic voltage feed forward. As a result, high-speed input voltage steps do not result in significant output voltage perturbations. In response to load current step increases, the ISL6264 will transiently raise the switching frequency so that response time is decreased and current is shared by two channels.
Protection
The ISL6264 provides overcurrent, overvoltage, and undervoltage protection as shown in Table 3. Overcurrent protection is tied to the voltage droop which is determined by the resistors selected as described in the "Component Selection and Application" section on page 18. After the load-line is set, the OCSET resistor can be selected to detect overcurrent at any level of droop voltage. An overcurrent fault will occur when the load current exceeds the overcurrent setpoint voltage while the regulator is in a 2phase mode. While the regulator is in a 1-phase mode of operation, the overcurrent setpoint is automatically reduced by half. For overcurrents less than 2.5 times the OCSET level, the over-load condition must exist for 120s in order to trip the OC fault latch. For overloads exceeding 2.5 times the set level, the PWM outputs will immediately shut off and PGOOD will go low to maximize protection due to hard shorts. In addition, excessive phase unbalance, for example, due to gate driver failure, will be detected in two-phase operation and the controller will be shut-down after one millisecond's detection of the excessive phase current unbalance. The phase unbalance is detected by the voltage on the ISEN pins if the difference is greater than 9mV.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6264 FAULT DUATION PRIOR TO PROTECTION Overcurrent fault Way-Overcurrent fault Overvoltage fault (1.8V) Overvoltage fault (+200mV) Undervoltage fault (-300mV) Unbalance fault (9mV) 120s < 2s immediately 1ms 1ms 1ms
PROTECTION ACTIONS PWM1, PWM2 three-state, PGOOD latched low PWM1, PWM2 three-state, PGOOD latched low
FAULT RESET VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle
Low-side FET on until Vcore < 0.85V, then PWMs three- VDD toggle state, PGOOD latched low (OV-1.8V always) ISL6264 still tries to regulate Vcore, PGOOD latched low VR_ON toggle or VDD toggle PWM1, PWM2 three-state, PGOOD latched low PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle
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Undervoltage protection is independent of the overcurrent limit. If the output voltage is less than the VID set value by 300mV or more, a fault will latch after one millisecond in that condition. The PWM outputs will turn off and PGOOD will go low. Note that most practical core regulators will have the overcurrent set to trip before the -300mV undervoltage limit. There are two levels of overvoltage protection and response. For output voltage exceeding the set value by +200mV for 1ms, a fault is declared. All of the above faults have the same action taken except 200mV overvoltage fault: PGOOD is latched low and the upper and lower power FETs are turned off so that inductor current will decay through the FET body diodes. This condition can be reset by bringing VR_ON low or by bringing VDD below 4V. When these inputs are returned to their high operating levels, a soft-start will occur. Under 200mV overvoltage fault, PGOOD is latched low but the ISL6264 still tries to regulate the output voltage. The second level of overvoltage protection behaves differently. If the output exceeds 1.8V, an OV fault is immediately declared, PGOOD is latched low and the low-side FETs are turned on. The low-side FETs will remain on until the output voltage is pulled down below about 0.85V at which time all FETs are turned off. If the output again rises above 1.7V, the protection process is repeated. This affords the maximum amount of protection against a shorted highside FET while preventing output ringing below ground. The 1.8V OV is not reset with VR_ON, but requires that VDD be lowered to reset. The 1.8V OV detector is active at all times that the controller is enabled including after one of the other faults occurs so that the processor is protected against highside FET leakage while the FETs are commanded off.
1.2V OFFSET --------------- R CIN R OFS
(EQ. 1)
Normally we chose RCIN as 1k for the convenience of design, then ROFS of 36.5k will result in a positive OFFSET voltage of 33mV.
Component Selection and Application
Soft-Start and VID Transition Slew Rates
The ISL6264 uses two different slew rates for start-up and the normal operation mode. The first is a slow slew rate in order to reduce inrush current during start-up. Note that the SOFT cap current is bidirectional. The current is flowing into the SOFT capacitor when the output voltage is commanded to rise, and out of the SOFT capacitor when the output voltage is commanded to fall. The two slew rates are determined by commanding one of two current sources onto the SOFT pin. As can be seen in Figure 30, the SOFT pin has a capacitance to ground. Also, the SOFT pin is the input to the error amplifier and is, therefore, the commanded system voltage. Depending on the state of the system, i.e. Start-Up or After Start-up, one of the two currents shown in Figure 30 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. These currents can be found under the "Soft-Start Current" section of the Electrical Specification Table.
ISL6264
Offset Voltage
The reference voltage at OFS pin is 1.2V. A resistor (ROFS) connecting the OFS pin to GND will setup a current flowing out of OFS pin. This current is internally mirrored out of FB pin. Therefore, a voltage drop is established across the resistor between FB and VDIFF pin. For the convenience of illustration, name the compensation network resistor between FB and VDIFF as RCIN.
Vo (V) C SOFT I SS I2 Error Amplifier + SOFT
+ V REF
OFFSET VID
FIGURE 30. SOFT PIN CURRENT SOURCES FOR FAST AND SLOW SLEW RATES
The first current, labelled ISS, is given in the Specification Table as 43A. This current is used during Soft-Start. The second current, I2 sums with ISS to get the larger of the two currents, labeled IGV in the Electrical Specification Table. This total current is typically 210A with a minimum of 185A. The symbol, SLEWRATE, will determine the choice of the SOFT capacitor, CSOFT, by Equation 2:
I2 C SOFT ----------------------------------SLEWRATE (EQ. 2)
0
Io (A)
FIGURE 29. LOAD LINE AND OFFSET
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Using a SLEWRATE of 4.2mV/s, and the typical I2 value, given in the Electrical Specification table of 230A, CSOFT is:
C SOFT ( 230A ) ( 4.2 ) (EQ. 3)
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core output voltage at a remotely sensed point. This allows the voltage regulator to compensate for various resistive drops in the power path and ensure that the voltage seen at the CPU die is the correct level independent of load current. The VSEN and RTN pins of the ISL6264 are connected to Kelvin sense leads at the die of the processor through the processor socket. These signal names are Vcc_sense and Vss_sense respectively. This allows the voltage regulator to tightly control the processor voltage at the die, independent of layout inconsistencies and voltage drops. This Kelvin sense technique provides for extremely tight load line regulation. These traces should be laid out as noise sensitive traces. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor must be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. To achieve optimum performance, place common mode and differential mode capacitor filters to analog ground on VSEN and RTN. Whether to need these capacitors really depends on the actual board layout and noise environment. Due to the fact that the voltage feedback to the switching regulator is sensed at the processor die, there exists the potential of an over voltage due to an open circuited feedback signal, should the regulator be operated without the processor installed. Due to this fact, we recommend the use of the Ropn1 and Ropn2 connected to VOUT and ground (illustrated in Figure 31). These resistors will provide voltage feedback in the event that the system is powered up without a processor installed. These resistors may typically range from 20 to 100.
A choice of 0.047F would guarantee a SLEWRATE of 3.7mV/s is met for minimum I3 value, given in the Electrical Specification Table. This choice of CSOFT will then control the Start-Up slewrate as well. One should expect the output voltage to slew to the VID value of 1.2V at a rate given by Equation 4:
I SS mV 43A dV ( S ) ------- = ------------------ = ---------------------- = 0.9 0.047F C SOFT dt (EQ. 4)
Selecting RBIAS
To properly bias the ISL6264, a reference current is established by placing a 147k, 1% tolerance resistor from the RBIAS pin to ground. This will provide a highly accurate, 10A current source from which OCSET reference current can be derived. Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor. Do not connect any other components to this pin as this would negatively impact performance. Capacitance on this pin would create instabilities and should be avoided.
Start-up Operation - PGOOD
The internal timer allows PGOOD to go high approximately 7.6ms after Vout reaches the target VID voltage during the start-up.
ISEN1 ISEN1 + INTERNAL TO ISL6264 + S + + 1RTN VDIFF + 1ISEN2 10A OC
ISEN2
OCSET VSUM + DROOP DFB DROOP
ROCSET
VO'
Iphase1
L1 CL1
+ Vdcr1DCR
VSUM Rseries VSUM
RS RL1 ISEN1 L2 RL2 ISEN2 VO'
RO1
Rdrp2
Iphase2 Rpar RS VSUM
VO' DCR Vdcr2+ RO2 Cbulk CL2 VO' ESR VOUT
Cn
VO' 0.018F 10 0.018F Ropn1
0.018F
Rdrp1
VSEN
to VOUT TO PROCESSOR SOCKET KELVIN CONNECTIONS
Ropn2
VCC_SENSE VSS_SENSE
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
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Rntc
ROCSET
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10A OC +
OC SE T
RS EQV = RS ------2
VS UM
VSUM INTERNAL TO ISL6264 + S + + 1+ 1+ DROOP DFB
DR OOP Rd rp2 + Cn VN -
DCR Vdcr EQV = I OUT x ------------2
VD IFF
RTN
VSEN
VO'
Rd rp1
( Rntc + Rseries ) x Rpar Rn = -------------------------------------------------------------------( Rntc + Rseries ) + Rpar
VO '
RO RO EQV = -------2 FIGURE 32. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM architecture. The switching frequency can increase during the application of a load to improve transient performance. It also varies slightly due changes in input and output voltage and output current, but this variation is normally less than 10% in continuous conduction mode. Refer to Figure 2. The resistor connected between the VW and COMP pins of the ISL6264 adjusts the switching window, and therefore adjusts the switching frequency. The RFSET resistor that sets up the switching frequency of the converter operating in CCM can be determined using the following relationship, where RFSET is in k and the switching period is in s. 6.81k sets about 300kHz switching frequency.
R FSET ( k ) ( period ( s ) - 0.4 ) 2.33 (EQ. 5)
For DCR sensing, the process of compensation for DCR resistance variation to achieve the desired load line droop has several steps and is somewhat iterative. The two-phase solution using DCR sensing is shown in Figure 31. There are two resistors connecting to the terminals of inductor of each phase. These are labeled RS and RO. These resistors are used to obtain the DC voltage drop across each inductor. Each inductor will have a certain level of DC current flowing through it, and this current when multiplied by the DCR of the inductor creates a small DC voltage drop across the inductor terminal. When this voltage is summed with the other channels DC voltages, the total DC load current can be derived. RO is typically 1 to 10. This resistor is used to tie the outputs of all channels together and thus create a summed average of the local CORE voltage output. RS is determined through an understanding of both the DC and transient load currents. This value will be covered in the next section. However, it is important to keep in mind that the output of each of these RS resistors are tied together to create the VSUM voltage node. With both the outputs of RO and RS tied together, the simplified model for the droop circuit can be derived. This is presented in Figure 32. Essentially one resistor can replace the RO resistors of each phase and one RS resistor can replace the RS resistors of each phase. The total DCR drop due to load current can be replaced by a DC source, the value of which is given by:
I OUT DCR V DCR_EQU = ------------------------------2 (EQ. 6)
In discontinuous conduction mode (DCM), the ISL6264 runs into period stretching mode. The switching frequency is dependent on the load current level. In general, the lighter load, the slower switching frequency. Therefore, the switching loss is much reduced for the light load operation, which is important for conserving the battery power in the portable application.
Static Mode of Operation - Static Droop Using DCR Sensing
As previously mentioned, the ISL6264 has an internal differential amplifier which provides very accurate voltage regulation at the die of the processor. The load line regulation is also accurate for both two-phase and single-phase operation. The process of selecting the components for the appropriate load line droop is explained here.
For the convenience of analysis, the NTC network comprised of Rntc, Rseries and Rpar, given in Figure 31, is labelled as a single resistor Rn in Figure 32. The first step in droop load line compensation is to adjust Rn, ROEQV and RSEQV such that sufficient droop voltage exists
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even at light loads between the VSUM and VO' nodes. As a rule of thumb we start with the voltage drop across the Rn network, VN, to be 0.5-0.8 times VDCR_EQU. This ratio provides for a fairly reasonable amount of light load signal from which to arrive at droop. The resultant NTC network resistor value is dependent on the temperature and given by
( R series + R ntc ) R par R n ( T ) = -----------------------------------------------------------R series + R ntc + R par (EQ. 7)
required to achieve the load line. Setting Rdrp1 = 1k_1%, then Rdrp2 is can be found using Equation 15:
2 R droop R drp2 = --------------------------------------------- - 1 R drp1 DCR G1 ( 25C ) (EQ. 15)
Droop Impedance (Rdroop) = 0.002 (V/A) as per the AMD specification, DCR = 0.0008 typical for a 0.36H inductor, Rdrp1 = 1k and the attenuation gain (G1) = 0.77, Rdrp2 is then:
2 R droop R drp2 = ------------------------------------- - 1 1k = 5.62k 0.0008 0.769 (EQ. 16)
For simplicity, the gain of Vn to the Vdcr_equ is defined by G1, also dependent on the temperature of the NTC thermistor.
Rn ( T ) G 1 ( T ) = --------------------------------------R n ( T ) + R sequ DCR ( T ) = DCR 25C ( 1 + 0.00393*(T-25) ) (EQ. 8)
Note, we choose to ignore the RO resistors because they do not add significant error. These designed values in Rn network are very sensitive to layout and coupling factor of the NTC to the inductor. As only one NTC is required in this application, this NTC should be placed as close to the Channel 1 inductor as possible and PCB traces sensing the inductor voltage should be go directly to the inductor pads. Once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. This is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the appropriate load line slope. To see whether the NTC has compensated the temperature change of the DCR, the user can apply full load current and wait for the thermal steady state and see how much the output voltage will deviate from the initial voltage reading. A good compensation can limit the drift to 2mV. If the output voltage is decreasing with temperature increase, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. The user should follow the evaluation board value and layout of NTC as much as possible to minimize engineering time. The 2mV/A load line should be adjusted by Rdrp2 based on maximum current, not based on small current steps like 10A, as the droop gain might vary between each 10A steps. Basically, if the max current is 40A, the required droop voltage is 84mV. The user should have 40A load current on and look for 84mV droop. If the drop voltage is less than 84mV, for example, 80mV. the new value will be calculated by:
84mV R drp2 = --------------- ( R drp1 + R drp2 ) - R drp1 80mV (EQ. 17)
(EQ. 9)
Therefore, the output of the droop amplifier divided by the total load current can be expressed as follows:
DCR 25 R droop = G 1 ( T ) ------------------- ( 1 + 0.00393*(T-25) ) k droop 2 (EQ. 10)
where Rdroop is the realized load line slope and 0.00393 is the temperature coefficient of the copper. To achieve the droop value independent from the temperature of the inductor, it is equivalently expressed by the following.
G 1 ( T ) ( 1 + 0.00393*(T-25) ) G 1t arg et (EQ. 11)
The non-inverting droop amplifier circuit has the gain kdroopamp expressed as:
R drp2 k droopamp = 1 + --------------R drp1 (EQ. 12)
G1target is the desired gain of Vn over IOUT. DCR/2. Therefore, the temperature characteristics of gain of Vn is described by:
1 1t arg et G 1 ( T ) = -----------------------------------------------------( 1 + 0.00393*(T-25) ) (EQ. 13)
For the G1 target = 0.76, the Rntc = 10k with b = 4300, Rseries = 2610k, and Rpar = 11k, Rseqv = 1825 generates a desired G1, close to the feature specified in Equation 20. The actual G1 at +25C is 0.769. For different G1 and NTC thermistor preference, the design file to generate the proper value of Rntc, Rseries, Rpar, and Rseqv is provided by Intersil. Then, the individual resistors from each phase to the VSUM node, labeled RS1 and RS2 in Figure 31, are then given by Equation 14.
Rs = 2 R seqv (EQ. 14)
Do not let the mismatch get larger than 600. To reduce the mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate factor. The appropriate factor in the example is 1404/853 = 1.65. In summary, the predicted load line with the designed droop network parameters based on the design tool is shown in Figure 33.
So, RS = 3650. Once we know the attenuation of the RS and Rn network, we can then determine the droop amplifier gain
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output voltage from going lower than the spec. This cap needs to be a high grade cap like X7R with low tolerance. There is another consideration in order to achieve better time constant match mentioned above. The NPO/COG (class-I) capacitors have only 5% tolerance and a very good thermal characteristics. But those caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10X to reduce the capacitance by 10X. But attention has to be paid in balancing the impedance of droop amplifier in this case.
2.25 LOAD LINE (mV/A)
2.2
2.15
2.1
2.05 0
20
40
60
80
100
INDUCTOR TEMPERATURE (C)
FIGURE 33. LOAD LINE PERFORMANCE WITH NTC THERMAL COMPENSATION
Dynamic Mode of Operation - Compensation Parameters
Considering the voltage regulator as a black box with a voltage source controlled by VID and a series impedance, in order to achieve the 2.0mV/A load line, the impedance needs to be 2.0m. The compensation design has to target the output impedance of the converter to be 2.0m. There is a mathematical calculation file available to the user. The power stage parameters such as L and Cs are needed as the input to calculate the compensation component values. Attention has to be paid to the input resistor to the FB pin. It is better to keep this resistor at 1k for the convenience of OFFSET design.
Dynamic Mode of Operation - Dynamic Droop using DCR sensing
Droop is very important for load transient performance. If the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. The output voltage could also take a long period of time to settle to its final value. This could be problematic if a load dump were to occur during this time. This situation would cause the output voltage to rise above the no load setpoint of the converter and could potentially damage the CPU. The L/DCR time constant of the inductor must be matched to the Rn*Cn time constant as shown in Equation 18:
R n RS EQV L ------------- = ---------------------------------- C n R n + RS EQV DCR (EQ. 18)
Static Mode of Operation - Current Balance using DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6264 through the matching of the voltages present on the ISEN pins. The ISL6264 adjusts the duty cycles of each phase to maintain equal potentials on the ISEN pins. RL and CL around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the ISEN voltages have minimal ripple voltage and represent the DC current flowing through each channel's inductor. For optimum performance, RL is chosen to be 10k and CL is selected to be 0.22F. When discrete resistor sensing is used, a capacitor most likely needs to be placed in parallel with RL to properly compensate the current balance circuit. ISL6264 uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6264 forces the ISEN voltages to be almost equal, the inductor currents will not be exactly equal. Take DCR current sensing as example, two errors have to be added to find the total current imbalance. 1) Mismatch of DCR: If the DCR has a 5% tolerance then the resistors could mismatch by 10% worst case. If each phase is carrying 20A then the phase currents mismatch by 20A*10% = 2A. 2) Mismatch of phase voltages/offset voltage of ISEN pins. The phase voltages are within 2mV of each other by current balance circuit. The error current that results is given by 2mV/DCR. If DCR = 1m then the error is 2A.
Solving for Cn, we now have Equation 19:
L ------------DCR C n = ---------------------------------R n RS EQV ---------------------------------R n + RS EQV (EQ. 19)
Note, RO was neglected. As long as the inductor time constant matches the Cn, Rn and RS time constants as given above, the transient performance will be optimum. As in the Static Droop Case, this process may require a slight adjustment to correct for layout inconsistencies. For the example of L = 0.36 H with 0.8m DCR, Cn is calculated below.
0.36H ------------------0.0008 C n = ------------------------------------------------------------------- = 330nF parallel ( 5.823k, 1.825k ) (EQ. 20)
The value of this capacitor is selected to be 330nF. As the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. If the output voltage transient has an initial dip (lower than the voltage required by the load line) and slowly increases back to the steady state, the cap is too small and vice versa. It is better to have the cap value a little bigger to cover the tolerance of the inductor to prevent the
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FN6359.1 October 16, 2006
ISL6264
In the above example, the two errors add to 4A. For the two phase DC/DC, the currents would be 22A in one phase and 18A in the other phase. In the above analysis, the current balance can be calculated with 2A/20A = 10%. This is the worst case calculation, for example, the actual tolerance of two 10% DCRs is 10%*sqrt(2) = 7%.
Fault Protection - Overcurrent Fault Setting
As previously described, the Overcurrent protection of the ISL6264 is related to the Droop voltage. Previously we have calculated that the Droop Voltage = ILoad * Rdroop, where Rdroop is the load line slope specified as 2mV/A in the AMD specification. Knowing this relationship, the over current protection threshold can be set up as a voltage Droop level. Knowing this voltage droop level, one can program in the appropriate drop across the Roc resistor. This voltage drop will be referred to as Voc. Once the droop voltage is greater than Voc, the PWM drives will turn off and PGOOD will go low. The selection of Roc is given in Equation 21. Assuming we desire an overcurrent trip level (Ioc) of 55A, and knowing from the Intel Specification that the load line slope (Rdroop) is 0.0021 (V/A), we can then calculate for Roc as shown in Equation 21.
I OC R droop 55 0.002 R OC = --------------------------------- = ------------------------- = 11.5k -6 10A 10 10 (EQ. 21)
Note, if the droop load line slope is not -0.002 (V/A) in the application, the over current setpoint will differ from predicted.
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FN6359.1 October 16, 2006
ISL6264
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06
4X 4.5 6.00 A B 6 PIN 1 INDEX AREA 31 30 36X 0.50 40 1 6 PIN #1 INDEX AREA
4 . 10 0 . 15 6.00
21 (4X) 0.15 20 TOP VIEW 40X 0 . 4 0 . 1 BOTTOM VIEW 11
10
0.10 M C A B 4 0 . 23 +0 . 07 / -0 . 05
SEE DETAIL "X" 0.10 C BASE PLANE SIDE VIEW ( 36X 0 . 5 ) SEATING PLANE 0.08 C C
0 . 90 0 . 1 ( 5 . 8 TYP ) ( 4 . 10 )
C ( 40X 0 . 23 ) ( 40X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN6359.1 October 16, 2006

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